Technical Training

As a leading player in the industry of semiconductor VLSI design, Oppstar also offer technical consultancy as well as training classes to cater to the needs of any party interested in IC Designs. With expertise in the area of ultra-deep sub-micron finFET technology, we are confident we are able to deliver only the best. The training classes are conducted by Senior/Staff design engineers with many years of experience in ultra-deep sub-micron finFET design. The training focuses not only on theories & design tools usage, but critically the experience that hands-on mini projects incorporated into the courses can provide. This training experience arms university alumni with the necessary set of soft skills and technical knowledge required when they step into the working society.

High Intensity Training for A High-Performing Workforce

IC Design Training Course:



  • Introduction to IC design
  • Design OS Environment
  • Programming : TCL, PERL
  • Linux Overview (Shell Scripting, Makefiles)
  • EDA Tools Overview (Elec. Design Automation)
  • IC Design Project Team Work and Management
  • Digital/ASIC Design Methodology Overview
  • Design for Fabrication Methodology Flow From Design to Fabrication

Digital Design

Digital Design

System Verilog

Digital Logic Design, Project Hands On

FPGA Implementation (Includes Verilog for synthesis)

Introduction to Verification Concept and Methodology

UVM: Universal Verification Methodology

Verification: VCS/ModelSim

Logic Synthesis: Design Compiler

  • Synthesis
  • Writing Timing Constraint
  • DFT (Design For Test)
  • Power Aware CPF & CLP
  • MTBF (Mean Time Between Failure)

Auto Place & Route Physical Implementation

  • Full chip Design Planning (Digital Partitions & EBBs Centric)
  • Block/Partition Design Floorplanning
  • Power Mesh Grids
  • Power Gated Design Implementation
  • Preplace cells and application
  • Place & Route Flow & Objective (Place, MBR, CTS, PostCTS, Route & PostRoute)
  • ECO (Engineer Change Order) Base vs Metal ECOs
  • Functional Equivalent Verification (FeV)
  • RC Extraction
  • Physical Verification

Static Timing Analysis -STA

  • Timing Path
  • Clocks (Prop clocks, skew, insertion delay, etc) relationship
  • Maxcap & Maxtrans
  • Setup & Hold
  • Recovery & Removal
  • Glitch
  • Corners, MCMMC (multi corner multi mode)

Power & SI Analysis: (Signal Integrity)

  • Static & Dynamic IR-Drop
  • SEM & S.H.E

Project: Logic Implementation (HDL to GDS)


Analog Design

Analog Design

CMOS Transistor Fundamentals

SPICE Language

Analog Circuit Design Theory

Analog Circuit Schematic, Design & Simulation

Analog Circuit Layout with Cadence Virtuoso

Physical Verification (LVS/DRC/Extraction)

  • Design Rule Check (DRC)
  • Layout vs Schematic (LVS) Methodology & Debug
  • Antenna Rule consideration and checks

Analog Design

  • Hierarchical Design
  • Testbenches
  • SDL
  • Spice Corners
  • Power/area/speed

Advance Layout with Cadence Virtuoso

  • Full Chip Design Planning (I/O Centric)
  • Physical Design & Signal Planning
  • Hierarchical Design
  • Standard cell library & Architecture
  • Embedded Block Design (EBB)
  • IO Buffer Layout Design
  • ESD (Electrostatic Discharge) Prevention & Latchup Phenomenon
  • Layout BKM   (Do's and Don't)
  • Parasitic Extraction


High Speed Digital Design Training Courses:

High Speed Digital Design

High Speed Digital Design

  • Basic fundamentals regarding the interaction of velocity, PCB material, capacitance, inductance, and characteristic impedance (Zo).
  • Rise and fall times of logic families, how to use an oscilloscope to measure ISI, jitter, eye diagrams, skin effect, SSO, SSN, and tan loss.
  • How to design a transmission line for Zo, proper termination for minimizing reflections, and how to layout a PCB-microstrip, stripline and differentials.
  • How to provide bypassing between power and ground and power delivery to the high-speed IC switching logic.
  • How to minimize crosstalk, via discontinuity and match cables/connectors for high-speed signal transmission.
  • How to control high speed clock and properly layout the bus structures (LVDS, multidrop, etc.)
  • All the details for laying out differential signaling for impedance control, minimizing reflections, and controlling EMI.

High Speed Digital High Density Board Design

High Speed Digital High Density Board Design

  • PCB Basics
  • PCB technology
  • Effective Floor Planning
  • Component selections
  • Technology Library / Environment Creation
  • Flow Methodology
  • Design Start Up
  • Power Delivery Stack Up
  • Component Orientation & Placement
  • Single-Ended Signaling Routing
  • Differential Signaling Routing
  • Critical Signal Routings
  • Verification & DRCs clean up
  • Manufacturing preparation
  • Vendor Documentation Preparation
  • High Density PCB Roadmap

High Speed Substrate Design Fundamental

High Speed Substrate Design Fundamental

  • Definition of Substrate Design                                                                                                                              
  • Package Technology                                                                                                                              
  • I/O Ring vs Package Planning
  • Technology Library / Environment Creation                                                                                                                              
  • Flow Methodology                                                                                                                               
  • Design Start Up                                                                                                                              
  • Power Delivery Stack Up                                                                                                                              
  • Critical Signal Routings ( SATA, PCIE, USB, Display )
  • Others  Critical signals (DDRs)                                                                                                                               
  • Prelim Design Review , Final Review & DRCs clean up.
  • Manufacturing preparation
  • Vendor Documentation Preparation
  • Package Roadmap & Products



Oppstar also provides training in collaboration with several other institutions:

AMCHAM - American Malaysia Chamber of Commerce   & USAINS - University of Science Malaysia